ECE 520.391/491: CAD of Digital VLSI Systems
Homework #4: Designing Inverters and Learning Verilog
From now on, we will use the following values for the Level 1 parameters of the transistors in 0.5um AMI process.
|
|
NMOSFET |
PMOSFET |
|
K (moCox) |
19.6 uA/V2 |
5.4 uA/V2 |
|
VTO |
0.74 V |
-0.74 V |
|
g |
0.6 |
0.6 |
|
l |
0.06 V-1 |
0.19 V-1 |
|
Xd (Under Diffusion) |
6 nm |
6 nm |
|
NSUB |
1.3 x 10^(16) cm-3 |
4.8 x 10^(15) cm-3 |
|
COX |
1.1 x 10^(-3) F/m2 |
1.1 x 10^(-3) F/m2 |
|
CGDO = CGSO |
6.6 x 10^(-12) F/m |
6.6 x 10^(-12) F/m |
|
CJ |
2.8 x 10^(-4) F/m2 |
3.0 x 10^(-4) F/m2 |
|
CJSW |
1.7 x 10^(-10) F/m |
2.6 x 10^(-10) F/m |
|
mb = msw |
0.5 |
0.5 |
|
fb = fsw |
1 V |
1 V |
|
Depth of Well |
|
5um |
P1: In class we constructed the derivation of the VIL, VIH, VLT, VOH, VOL, NML, NMH, Tr and Tf for an inverter. Derive the expression for these parameters for the inverter in P1. Using the W/L, and the voltages in the figure, compute these specifications for this inverter.
P.1
P2: Design a CMOS inverter with the following specifications: VLT = 3V, Tr < 2ns and Tf < 2ns if the load capacitance is 100fF. Show the hand calculations used to get the W/L for the transistors. Draw the schematic of the inverter and create a symbol. Simulate the inverter schematic. Plot the DC and transient characteristics and verify that the specifications were met. Draw the layout of this inverter. Try to make the layout as tight as possible. Measure the size of the layout. Run a DRC, extract the layout and LVS the design. Run a simulation on the extracted view and measure the specifications. How well do they match the schematic specs? Write a behavioral Verilog model for inverter including the measured propagation delay from the simulation of the extracted view. Verify that the inverter simulates in Verilog.
P3: Create a ring oscillator by connecting 11 inverters in a loop. Simulate the ring in both specterS and Verilog. Create the layout of the ring, run a DRC and LVS. Simulate the extracted view of the ring.