ECE 520.491: CAD of Digital VLSI Systems

Homework #2: Understanding the transistor, Cadence schematic, layout and verification

P1: In this homework, you have to extract hand calculation parameters from spice simulations such that your hand calculations will match your simulations results. For each part, print the graphs that you used to measure the parameter. Explain clearly how you extracted the parameters.

a. Open a library and a schematic cell called NMOS_param. In this cell, draw a schematic, using a 4 terminal NMOSFET W=3.5u, L=3.5u, that will allow you to sweep the voltages on the gate, drain, source and bulk. Print this schematic.

b. Holding the Vds = 5V, Vsb=0V, run a DC simulation that will sweep the Vgs of the transistor from 0V - 5V, in steps of 0.01V. Using the calculator tool, plot SQRT(Ids) vs Vgs. Extract the values of Vton and Kn.

c. Repeat for a PMOSFET, by replacing Vgs -> Vsg, Vds - >Vsd, Vsb - >Vbs and Vton -> Vtop.

d. Go to the MOSIS website and download the latest SPICE parameter sheets for the 0.5um AMI process. From the sheets, determine the values for: COX, CGDO, CGSO, CJ, CJSW and all the interconnect overlap capacitances.

e. Draw the layout of NMOS transistor with W = L= 7um. Run DRC, Extract and run a LVS. Print layout and results of DRC and LVS.

f. Repeat (e) for a PMOS.