ECE 520.491:  CAD of Digital VLSI Systems

Dr. Ralph Etienne-Cummings

 

CPU Design Project

(Teams of 4 students)

 

 

In class I presented an architecture for the basic 16 bit RISC computer.  I outlined the organization of the registers, the format of instruction, the list of instructions, the timing sequence for each instruction and the flow chart for operation.  You can find the discussion in "Computer System Architecture," by Morris Mano.  I have also posted the relevant notes.  You are to redesign this computer with the following specifications:

 

(1)     The addressable memory must be 65,536 lines of 24-bits.

(2)     Memory is external to the CPU chip (Find an appropriate 64K x 24b memory chip.  Take into consideration the time required to read and write to the memory.).

(3)     The bus width must be 24-bits wide.

(4)     The CPU chip only has 60 pins for all I/O (clocks, instruction fetch, operand fetch, results store, test and trouble-shooting pins).  Four additional power pins are available.

(5)     AC, DR, PC, AR, GP1, GP2, GP3, GP4 registers must allow load, clear

(6)     AC, DR, PC and AR must allow increment.

(7)     AC & DR must allow shifts (left and right)

(8)     Including the following new ALU functions:  OR, XOR, NEG (two’s complement) and SUB (subtract)

(9)     Add a new addressing modality that allows immediate operands.

 

 

Below are the target dates for each part.  All final presentations will take place on December 11th, 2007.

 

Part 1:  Presentation (Power Point, 20 minutes) due Wednesday November 14th, 2007:  Form a team of four members.  Outlined the organization of the registers, the format of instruction, the list of instructions, the timing sequence for each instruction, the flow chart of operation and the chip pin-out assignment for this new 24-bit computer.

 

Part 2:  Presentation (Power Point, 20 minutes) due Tuesday November 20th, 2007:  Design all the registers for your CPU.  Make sure that the design is compatible with your busing scheme.  Construct the design with basic gates that have both schematic and behavioral views.  Show Spice and Verilog simulation of the complete module, indicating the maximum speed of the module.  Draw the layout of the module. DRC and LVS it. 

 

Part 3:  Presentation (Power Point, 20 minutes) due Wednesday November 28th, 2007:  Design your ALU or your major processing core for your project.  Make sure that the design is compatible with your busing scheme and registers.  Construct the design with basic gates that have both schematic and behavioral views.  Show schematic and Verilog simulation of the complete module, indicating the maximum speed of the module.  Draw the layout of the module. DRC and LVS it.

 

Part 4:  Presentation (Power Point, 20 minutes) due Wednesday December 4th, 2007:  Design the complete control unit for the CPU.  Interface the control unit to the counters, decoders, selectors and registers.  Draw the layout of the module.  DRC and LVS it.  At this point you should be near completion of the CPU. 

 

Part 5:  Final Presentation (Power Point, 30 minutes) due Wednesday December 11th, 2007:  In this presentation you are to outline you design, show simulation results, predict operation specifications, report on completion rate, indicate what, if any thing, is required to complete the design.