520.391/491: CAD Design of Digital VLSI Systems I
Fall 2007
Dr. Ralph Etienne-Cummings
Email: retienne@jhu.edu
Office: Barton 401B
Class Time: TW,
Office Hrs: TW 3:00 – 5:30PM Barton 401B
URL: http://etienne.ece.jhu.edu/~etienne/ECE491.html
Class Announcements - Refresh this page often!
11/8 – Computer Organization notes added
11/8 – Sample Exam 2’s added to old exam link
11/7 – Final Project posted.
10/30 – HW5 posted Due date is 11/7.
10/17 – HW4 posted Due date is 10/24.
9/28 – Exam 1 is on Wednesday 10/3 in class.
9/28 – Sample Exams link is up
9/28 – Design Rules link added
9/27 – TA office hours posted.
9/19 – Lecture notes page added
9/19 – HW2 posted. Due date is 9/28.
9/12 – The Class newsgroup is here.
9/12 – Link posted for more thorough discussion of device physics under Reading Material.
9/12 – Class online group formed you should receive an invitation by the end of the day if not email Andre.
9/12 – HW1 posted. Due date is 9/19
9/7 - For access to the grad computer lab, please see Candace Abel or Ethel Peterson in Barton 105 (Note: you must be on the class roster).
9/7 - Click here for instructions on running Cadence from home
9/7 - IEEE Code of Ethics
9/7
- Please click on the following link and register for an account.
http://www.ece.jhu.edu/acct_req.htm
Homeworks:
HW1 due 9/19.
HW2 due 9/28.
HW4 due 10/24.
HW5 due 11/7.
Submit by email to Andre at vinfluxbeing@gmail.com
Course Outline:
Abstract:
This course is an introduction to VLSI design. Although the emphasis is on digital
VLSI circuits, an initial overview of the analog basis of digital VLSI circuits
will be given. Using a state-of-the-art CAD environment provided by CADENCE
Design Systems, the students will design combinational and sequential circuits
at various levels of abstraction.
First
a brief discussion of the device physics of MOSFETs will be presented. Next,
CMOS circuits will be used to construct digital primitives such as NOT, NAND,
NOR, FLIP-FLOP etc... These circuits will be analyzed using hand calculations
and SPICE/SPECTER simulations. Subsequently, the integration of these
primitives using the SCMOS design rules provided by MOSIS will be discussed. A
brief overview of the fabrication steps and justifications for the rules will
also be provided. Schematic versus layout verification and SPICE simulation
will be used to confirm the integrity of the mask layout. Next the behavioral
abstraction of the circuits using VERILOG HDL will be developed. The behavioral
model will include the effects of the parasitic components encountered in the
layout process. Using the behavioral models, a large system will be developed
for the class project. The project, which will be defined later, will be
integrated into a TINY Chip in 0.5um Nwell CMOS process. The entire chip will
be simulated, verified and converted to CIF for possible submission to the
MOSIS service for fabrication.
Textbooks:
Digital Integrated Circuits, J. Rabaey, 2003, ISBN 0-13-090996-3
Recommended:
Verilog HDL: A guide to digital design and synthesis, S. Palnikar, 1996, ISBN
0-13-451675-3
Computer Systems Architecture, M. Mano, 1995, ISBN 0-13-175563-3
Other References:
Basic VLSI Design, D. Pucknell and K. Eshraghian 1988
Fundamentals of CMOS VLSI Design, J. Uyemura, 1988
Analysis and Design of Analog integrated Circuits, P. Gray and R. Meyer, 1994
Modern VLSI Design, Wayne Wolf, 1994
CAD: CADENCE SPICE VLSI circuit simulators
SPECTER VLSI circuit simulators
VERILOG-XL Logic/VHDL simulator
CADENCE Design Tools for complete design integration, verification and
submission in CIF format via the Intenet
Cadence Manual Documents, Techfiles and Other Helpful
Files
Our Cadence Page
Course Grading:
Weekly Homework 30%
Exam1: 10%
Exam2: 20%
Project: 40%
Grading Policy:
90% or above A
80% to 89% B
65% to 79% C
45% to 64% D
44% or below F
Schedule
|
Dates (week beginning) |
Topics |
|
September 9 |
Course Introduction
Device Physics of
MOSFETS: Chapter 3-4 Intro. to Cadence
Design Environment |
|
September 16 |
Device Physics of MOSFETS: Chapter 3 |
|
September 23 |
Device Physics of
MOSFETS: Chapter 3 Introduction to Layout
and VerilogHDL |
|
September 30 |
The
Wire: Chapter 4 The inverter:
Chapter 5 Exam 1 |
|
October 7 |
The
Wire: Chapter 4 The inverter:
Chapter 5 |
|
October 14 |
Combinational Logic
Gates: Chapter 6 |
|
October 21 |
Combinational Logic
Gates: Chapter 6 |
|
October 28 |
Combinational Logic
Gates: Chapter 6 Sequential Logic
Circuits: Chapter 7 |
|
November 4 |
Basic Computer
Design: A Hardware Perspective (Final Project
assignment) Exam 2 |
|
November 11 |
Current Issues in Computer
Design |
|
November 18 |
Arithmetic Building
Blocks: Chapter 11 (cont.) Memory and Arrays: Chapter 12 |
|
November 25 |
Memory and Arrays: Chapter 10 (cont.) |
|
December 2 |
Interconnections/Timing:
Chapter 9/8 Projects Consulting |
|
December 9 |
Final Project
Presentations |
Class Notes and Handouts:
Lecture Notes
Reading Material:
Homework Solutions:
Old Exams:
Teaching Assistant and Cadence Support
Andre Harrison (aharri68@jhu.edu)
Barton 401 (Computational Sensory-Motor Systems Lab)
Tel: x6-0746
Office Hours: Thursdays 5pm - 7pm
Fridays 3pm - 5pm
(Or just drop by if you have a question.
If I’m not there send an email.)
Linux Support
Justin Martin, Brian O’Reilly (ecehelp@jhu.edu)