.




.
.
Information
Projects
People
Publications
Links
News
Videos and Presentations
Sponsors

Integrate and Fire Array Transceiver


The brain performs complex computations by operating a large number of relatively simple neurons in parallel, with a high degree of interconnectivity between cells. Because many features of this processing power emerge from the network architecture, it is useful to generate computational models of potential configurations to explain experimental observations and stimulate future work. Traditionally, these simulations are generated in software and executed over the course of a few hours. However, if we are to build autonomous devices that emulate the operation of the brain, our circuits must function in real-time. Additionally, we are interested in creating an interface between the simulations and biology to evaluate their function in situ, and this will also require real-time operation.

Previously, we designed and implemented a reconfigurable hardware network (the IFAT) of 2,400 neurons that is capable of operating in real-time. A mixed-signal design, the IFAT (integrate-and-fire array transceiver) performs analog computations internally, while communicating with the external world in the digital domain. To allow unlimited connectivity and reprogrammability, there are no hardwired connections between neurons. Instead, network topologies and synaptic parameters are stored in a look-up table in off-chip RAM, and a microcontroller is responsible for routing action potentials to their appropriate targets. To achieve high throughput and ensure interoperability with other neuromorphic chips, the digital communication protocol known as address-event representation (AER) is used both between neurons in the IFAT and between the IFAT and external hardware.

IFAT
Integrate-and-Fire Array Transceiver System

In the current phase of the project, we are designing a new chip. The neurons and synapses on this new IFAT will more closely emulate biology by having temporal dynamics for a more bio-realistic implementation and shunting inhibition. Temporal dynamics and shunting are important synaptic properties that are thought play a role in learning neural codes and encoding spatio-temporal patterns of spikes. Without temporal dynamics, the neuron is insensitive to absolute time. In biology, this is achieved by subjecting the neurons to leakage currents. The rate of this leakage defines the time constant of the system, without which the neuron is insensitive to absolute time. Shunting affects some known complex nonlinear interactions between synaptic inputs which is important in the visual cortex. The IFAT will be used to implement a biologically plausible model of visual information processing.

The new chip design will also carry more neurons that its predecessor and it will be embedded into a new environment. This new system will use high speed USB and a soft-CUP that make it smaller and easier to handle than the existing version. The new system will be able to handle up to 60'000 artificial neurons and C++ code will allow the CPU on the FPGA to modify the look up tables on the run which allows the implementation of learning rules.