Integrate and Fire Array Transceiver (IFAT)

The brain performs complex computations by operating a large number of relatively simple neurons in parallel, with a high degree of interconnectivity between cells. Because many features of this processing power emerge from the network architecture, it is useful to generate computational models of potential configurations to explain experimental observations and stimulate future work. Traditionally, these simulations are generated in software and executed over the course of a few hours. However, if we are to build autonomous devices that emulate the operation of the brain, our circuits must function in real-time. Additionally, I am interested in creating an interface between the simulations and biology to evaluate their function in situ, and this will also require real-time operation. Therefore, with assistance from my advisor, I designed and implemented a reconfigurable hardware network of 2,400 neurons that is capable of operating in real-time.

A mixed-signal design, the IFAT performs analog computations internally, while communicating with the external world in the digital domain. To allow unlimited connectivity and reprogrammability, there are no hardwired connections between neurons. Instead, network topologies and synaptic parameters are stored in a look-up table in off-chip RAM, and a microcontroller is responsible for routing action potentials to their appropriate targets. To achieve high throughput and ensure interoperability with other neuromorphic chips, the digital communication protocol known as address-event representation (AER) is used both between neurons in the IFAT and between the IFAT and external hardware. 

The IFAT chip builds upon an earlier design by David Goldberg. The IFAT PCB was constructed with the help of Udayan Mallik, who also designed and tested the microcontroller firmware. A description of some components of this work has been submitted for publication.  Click here to see my journal club presentation on this work, or here for my presentation at the 2003 NIPS Workshops, or here for my ISCAS'04 presentation.