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Focal-Plane Spatial Processing and the Computation-On-Readout (COR) Architecture

In the late 1990's we developed an alternative to pixel-parallel imaging processing. The latter had been the predominant approach for focal-plane neuromorphic image processing. We called it the Computation-On-Readout (COR) architecture. It married the pixel serial image processing techniques used in traditional computer vision with the pixel parallel approach. This approach used block parallel processing on an image which is scanned serially. With the appropriate scanning hardware and programmable computational units, this processing technique can be configured to realize any scanning technique, uses very low-power and can be used to implement a variety of image processing computation at the focal-plane while using a small area (<10% of focal plane area, and scales to smaller a ratio for larger arrays). This processing technique allows for high resolution imaging and computation with little temporal penalty. Using this technique, we have implemented reconfigurable orientation selective receptive fields,1 motion estimation,2 stereo imaging,3 and color-based object recognition.4 Lastly, we have also developed various new architectures for CMOS imagers, some ideal for COR processing, and have co-edited a book on the subject.5

References

  1. ["Real-Time Image Processing using a Spiking Imager and an Integrate-and-Fire Array Transceiver System," accepted to Neural Computation, Fall 2006; "Implementation Of Steerable Spatiotemporal Image Filters on the Focal Plane," IEEE Trans. Circuits and Systems-II, Vol. 49, No. 4, pp. 233-244, April 2002; "High Performance Biomorphic Image Processing Under Tight Space and Power Constraints," Autonomous Robots, Vol. 11, No. 3, pp. 227-232, November 2001; &qout;Programmable Spatial Processing Imager Chip," Electronic Letters, Vol. 37, No. 11, pp. 688-690, May, 2001; "A Programmable Focal-Plane MIMD Image Processor Chip" IEEE J. Solid-State Circuits, Vol. 36, No. 1, pp 64-73, January 2001]
  2. ["CMOS Pixel-Level ADC with Change Detection," accepted to IEEE J. Solid-State Circuits, Spring 2007; "A Simplified Normal Optical Flow CMOS Camera," IEEE Trans. Circuits and Systems-I, Vol. 53, No. 6, pp. 1223-1234, June 2006; "Normal Optical Flow CMOS APS Imager," IEE Electronics Letters, Vol. 41, No. 13, pp. 732-733, June 2005; "Bearing Angle Estimation for Sonar Micro-Array Using Analog VLSI Spatiotemporal Processing," IEEE Trans. Circuits and Systems-I, Vol. 53, No. 4, pp. 769-783, 2006; "Sensing Signal Input Bearing to a Sensor Array Using Velocity-Sensitive Spatiotemporal Filters," IEE Electronics Letters, Vol. 40, No. 3, pp. 211-212, February 2004; "A Pipelined Temporal Difference Imager," IEEE J. Solid-State Circuits, Vol. 39, No. 3, pp. 538-543, March 2004; "High Performance Biomorphic Image Processing Under Tight Space and Power Constraints," Autonomous Robots, Vol. 11, No. 3, pp. 227-232, November 2001; R. Etienne-Cummings, "Neuromorphic Visual Motion Detection in VLSI," Int. J. Computer Vision, Vol. 44, No. 3, pp. 175-198, September 2001; "Hardware Implementation of a Visual Motion Pixel using Oriented Spatiotemporal Neural Filters," IEEE Trans. Circuits and System II, Vol. 46, No. 9, pp. 1121-1136, 1999]
  3. ["A Linear and Low-Noise Current Domain Imager," accepted to IEEE J. Solid-State Circuits, Spring 2007; "A Single Chip Stereo Vision System," Analog Integrated Circuits and Signal Processing Journal, Vol. 7, pp. 703-712, July 2004; "A Single Chip Stereo Imager" ISSCC '06 Digest of Technical Papers, Vol. 49, Feb 2006]
  4. ["A Vision Chip for Color Segmentation and Object Recognition," EURASIP J. Applied Signal Processing, Vol. 2003, No. 7, pp. 703-712, June 2003. (Best Paper 2003); "Single Chip for Color Segmentation, Histogramming and Object Recognition," ISSCC'02 Digest of Technical Papers, Vol. 45, Feb 2002] 10["CMOS Pixel-Level ADC with Change Detection," accepted to IEEE J. Solid-State Circuits, Spring 2007; "A Linear and Low-Noise Current Domain Imager," accepted to IEEE J. Solid-State Circuits, Spring 2007; CMOS Imagers: from Phototransduction to Image Processing, Kluwer Academic Publishers, Spring 2004; "An Address Event Digital Imager," IEEE J. Solid-State Circuits, Vol. 38, No. 2, pp. 281-294, February 2003; "Arbitrated Address Event Representation Digital Image Sensor," ISSCC '01 Digest of Technical Papers, Vol. 44, pp. 92-93, Feb 2001; "Dual Pixel Array for Imaging, Motion Detection and Centroid Tracking," IEEE Sensors Journal, Vol. 2, No. 6, pp. 529-548, December 2002; E. Culurciello, R. Etienne-Cummings, and K. Boahen, "An Address Event Digital Imager," IEE Electronic Letters, Vol. 37, No. 24, pp. 1443-1445, November, 2001; "Single-Capacitor-Single-Contact Active Pixel," IEEE ISCAS 2000, Geneva, Switzerland, May 2000]