Cadence Techfiles For MOSIS SCMOS Process

This are techfiles for the MOSIS SCMOS processes.

During DRC, Extract and LVS, set the switches available to your particular process.

Resistors, Capacitors and Diodes will be extracted when the structures are also covered by one of the three appropriate layers. I do not guaranty that the extracted values are correct, so please verify and modify the scale factor.

ASCII Techfile and Rules Files

mosis.tf
divaDRC.rul
divaEXT.rul
divaERC.rul
display.drf
layerMap.mosis


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Last modified: Sep. 27, 2003