Cadence Techfiles For MOSIS SCMOS Process
This are techfiles for the MOSIS SCMOS processes.
During DRC, Extract and LVS, set the switches available to your
Resistors, Capacitors and Diodes will be extracted when the structures are also covered by one of the three appropriate layers. I do not guaranty that the extracted values are correct, so please verify and modify the scale factor.
ASCII Techfile and Rules Files
"Information is provided "as is" without warranty or guarantee of any kind.
No statement is made and no attempt has been made to examine the information, either
with respect to operability, origin, authorship, or otherwise.
Please use this information at your own risk--and any attempt to use this information
is at your own risk--we recommend using it on a copy of your data to be sure you
understand what it does and under what conditions. Keep your master intact until you
are personally satisfied with the use of this information within your environment."
Cadence® is a trademark of Cadence Design
Systems, Inc., 555 River Oaks Parkway, San Jose, CA 95134
For web related questions contact: Viktor Gruev
Last modified: Sep. 27, 2003