CAD of Digital VLSI Systems

Homework #1: Understanding the IC Technology, MOSIS and the Transistor

P1: Go to the MOSIS <www.mosis.org> website and find answers to the following questions

(a) What are the various IC foundries that offer their services through MOSIS.

(b) What are the feature sizes of the available fabrication processes.

(c) How much does each process cost for a 5mm x 5mm chip.

(d) Assuming that each transistor occupies an area of 12L x 16L, where L is (feature size)/2. How many transistors can be placed in each 5mm x 5mm chip offered by MOSIS.

(e) Which process offers the best transistor/dollar ratio?

(f) List the various design rules sets that can be used with the 0.5um AMI process.

(g) Obtain the model files for NMOS and PMOS transistors from the latest AMI 0.5um run

(h What is the value of COX, mobility and threshold voltage for the NMOS and PMOS transistors in the latest AMI 0.5um run.

(i) For the latest AMI 0.5um determine the capacitance between two 1mm long conductors, implemented with minimum width Poly1 and Metal3, drawn directly on top of each other.

P2: Go to the Cadence Tutorial Webpages at: http://etienne.ece.jhu.edu/cadence/manual/index.html and perform all the tasks indicated in the manual. Please generate a lab report showing: a) A schematic of an inverter, b) a symbol, c) DC and Transient simulations of the inverter, d) a layout of the inverter, e) the DRC results, f) an extracted view, g) the LVS results, h) the DC and Transient Simulations of the extracted view of the inverter, i) a behavioral model for the inverter and j) Verilog simulation results for the invert.